April 24,$Taiwan Semiconductor (TSM.US)$The 2024 North American Science and Technology Symposium was held. Many cutting-edge technologies were showcased at the conference, which attracted market attention.

J.P. Morgan Chase said in its latest report on the 26th that the highlights of the summit include the launch of the A16 process node, the debut of advanced packaging technology SoW, and further innovation in silicon photonics technology. The report highlights TSMC's technological leadership in the AI era, and provides an “increase in wealth” rating and a target price of NT$900.

TSMC first introduced the A16 process node at its North American technical seminar, which is its first integrated nanosheet transistor and back-powered node using the TSMC superpower rail architecture. The A16 is expected to be in production in 2026 and is ideal for certain high performance computing (HPC) applications, particularly those that benefit from higher clock speeds. A16 is likely an extension of the N2 family, following N2 and N2P/N2X. The A16's PPA (performance, power consumption, area) gain is significant and is expected to continue to drive demand from fabless customers for the N2 family, particularly in the HPC and AI fields.

Use of A14 process nodes and high NA EUV

A14 is an independent new process node outlined by TSMC in its annual report. It is expected to use second-generation nanosheet transistors and more advanced back-side power supply networks, bringing full node PPA advantages. Production of the A14 is likely to begin in 2027-28. As an extension of the N2 family, the A16 will not use high NA EUV tools. For A14, TSMC may consider using some high-NA EUV tools, but due to ecosystem preparation (photoresist, mask size expansion, throughput in actual production scenarios), the possibility of widespread use is quite limited.

The next step in advanced packaging technology: SoW

TSMC also debuted its wafer-level system (SoW) product, which allows packaging of a large number of chips (logic chips, composite SoIC packages, HBM, and others), as well as power and thermal modules on a full 12-inch silicon wafer scale. This will be a significant increase in the complexity and capability of advanced packaging compared to CoWOS and 3DSoIC, as the entire computing system may be packaged in a single wafer.

Further innovation in silicon photonic technology

TSMC announced the development of its photonic engine (COUPE) to enable the stacking of photons and electronic chips to drastically reduce energy consumption and impedance. TSMC is expected to lead the development of co-packaged optical technology in 2026. This is consistent with TSMC's views as key partners of Broadcom and Nvidia, two companies currently leading in advanced co-packaging optical technology.

N2 nanoFlex, N4C, and automotive advanced packages

TSMC announced the availability of Nanoflex for N2, an extension to FinFlex announced in N3. This allows customers to mix different types of transistors in the same chip to balance performance, power consumption, and density. TSMC also announced N4C, which will achieve a 9% reduction from N4P to reduce costs for cost-sensitive applications in 2025. Finally, automotive SoCs and ADAS chips are also moving to advanced packaging, and TSMC has begun providing Info and Cowos-R solutions for ADAS chips and SoCs.

Conclusion: TSMC will continue to lead for 3-5 years

Based on the above reasons, J.P. Morgan Chase rated TSMC as an “increase in holdings”, and the target price was NT$900.

The J.P. Morgan report highlights TSMC's leading position in technological innovation and advanced packaging, as well as its key role in the AI era. Through a series of technological breakthroughs, TSMC is expected to maintain its leading position in the semiconductor industry for years to come.

Editor/Somer